diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv
index d48d1e1..1497be9 100644
--- a/Labs/01. Adder/tb_fulladder.sv	
+++ b/Labs/01. Adder/tb_fulladder.sv	
@@ -40,8 +40,6 @@ module tb_fulladder();
     initial begin
         $timeformat(-9, 2, " ns");
 
-        #1; // wait initial line_dump
-
         $display("START simulation of 1-bit fulladder.");
         $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
         $display("If you don't see the message then click the button 'Run All'");
diff --git a/Labs/01. Adder/tb_fulladder32.sv b/Labs/01. Adder/tb_fulladder32.sv
index 6049afa..58ff259 100644
--- a/Labs/01. Adder/tb_fulladder32.sv	
+++ b/Labs/01. Adder/tb_fulladder32.sv	
@@ -44,8 +44,6 @@ module tb_fulladder32();
     initial begin
         $timeformat(-9, 2, " ns");
 
-        #1; // wait initial line_dump
-
         $display("START simulation of 32-bit fulladder.");
         $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
         $display("If you don't see the message then click the button 'Run All'");
diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv
index 710904e..a247b7e 100644
--- a/Labs/01. Adder/tb_fulladder4.sv	
+++ b/Labs/01. Adder/tb_fulladder4.sv	
@@ -44,8 +44,6 @@ module tb_fulladder4();
     initial begin
         $timeformat(-9, 2, " ns");
 
-        #1; // wait initial line_dump
-
         $display("START simulation of 4-bit fulladder.");
         $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
         $display("If you don't see the message then click the button 'Run All'");