ЛР4. Обновление тестбенча

Замена reg и wire, исправление нейминга сигналов, способов установки
задержек, а также уменьшен интервал вводимых чисел для уменьшения длины
временной диаграммы.

Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv

@@ -10,32 +10,39 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 */
 module lab_04_tb_CYBERcobra();
 
+  logic [31:0]  OUT;
+  logic         clk;
+  logic         rst;
+  logic [15:0]  sw_i;
+
+
   CYBERcobra DUT(
     .clk_i(clk),
-    .rst_i(rstn),
+    .rst_i(rst),
     .sw_i (sw_i),
     .out_o(OUT)
   );
 
-    wire [31:0] OUT;
-    reg clk;
-    reg rstn;
-    reg [15:0] sw_i;
-
   initial clk <= 0;
-    always #5 clk = ~clk;
+  always #5ns clk = ~clk;
 
   initial begin
+    logic [15:0] count_num;
     $display("Test has been started");
-    rstn = 1'b1;
+    rst = 1'b1;
-    #10;
+    repeat(2)@(posedge clk);
-    rstn = 1'b0;
+    rst = 1'b0;
-    sw_i = 16'b100001000; //значение, до которого считает счетчик
+    count_num = $urandom_range(5, 10);
-    #10000;
+    sw_i = count_num;
-    $display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
+    repeat(count_num * 2 + 15) begin
+      @(posedge clk);
+    end
+    $display("\nThe test is over.");
+    $display("See the internal signals of the CYBERcobra on the waveform");
     $finish;
-    #5;
+    @(posedge clk);
-    $display("You're trying to run simulation that has finished. Aborting simulation.");
+    $display("You're trying to run simulation that has finished.");
+    $display("Aborting simulation.");
     $fatal();
   end