diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
index 85a2bf6..82db55c 100644
--- a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv	
+++ b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv	
@@ -26,12 +26,12 @@ reg minus;
 
 alu_riscv DUT
 (
-  .ALUOp  (operator_i),
-  .A      (operand_a_i),
-  .B      (operand_b_i),
+  .alu_op_i (operator_i),
+  .a_i      (operand_a_i),
+  .b_i      (operand_b_i),
 
-  .Result (result_o),
-  .Flag   (comparison_result_o)
+  .result_o (result_o),
+  .flag_o   (comparison_result_o)
 );
 
 assign operator_i  = SW[4:0];
@@ -93,4 +93,4 @@ always @(posedge CLK100) begin
     end
 end
 
-endmodule
\ No newline at end of file
+endmodule